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1. Field of Invention
The invention relates to analog-to-digital (A/D) conversion, particularly to high-speed A/D conversion with reduced component cost.
2. Description of Prior Art
Prior art techniques for A/D conversion are numerous, but fall into a number of general classes, among which are parallel or flash conversion, successive approximation conversion, slope integration conversion, and discrete charge-balancing conversion.
Parallel conversion, also known as flash conversion, is typically the fastest technique, but has the highest implementation cost. In an N-bit A/D converter, there are 2N possible digital number outputs. A total of 2Nxe2x88x921 boundaries define the analog input ranges corresponding to the digital number outputs. In parallel conversion; 2Nxe2x88x921 analog reference signals which are the bin boundaries are generated. An input is simultaneously compared to each reference signal. The 2Nxe2x88x921 comparators produce digital output signals which are decoded to produce the desired digital output number.
Flash conversion is fast because the input-to-output delay includes the reaction times of one comparator stage and the subsequent decoding logic. Flash conversion is costly to implement, because the number of analog reference signals and comparators grows exponentially with N.
Successive approximation (SA) A/D conversion is considerably slower than flash A/D conversion, but has a much lower implementation cost for large N. In successive approximation, a tree search is performed on the possible digital output numbers. The tree search proceeds in a sequence of approximation stages. At each stage, a possible digital output number is passed to an N-bit digital-to-analog (D/A) converter, which produces a corresponding analog value. This value is compared to the analog input signal. The result of the comparison is used to select a new possible digital number value for the following stage.
With respect to components, an N-bit SA-based A/D converter requires one comparator, an N-bit D/A converter, and logic circuits for directing the search and storing the results. The converter and the comparator can be re-used for each stage of the search. The speed of the SA converter depends on N and on the settling times of the comparator, the D/A converter, and the logic circuits. For instance, a 16-bit SA A/D conversion would require 16 comparisons of 16 separate 16-bit D/A conversion results, while an 8-bit SA A/D conversion would require only 8 comparisons of 8 separate D/A conversion results.
A prior art hybrid is the half-flash A/D converter, which has intermediate speed and component cost relative to flash and SA converters. In an N-bit half-flash converter, a first stage N/2-bit flash conversion is performed to obtain the values of the N/2 most-significant bits of the desired digital output number. These bit values are passed to an N/2-bit D/A converter, which provides a gross reconstruction of the analog input. The gross reconstruction is subtracted from the analog input, and the resulting difference is passed to a second N/2-bit flash converter, which produces the N/2 least-significant bits of the desired digital output number.
Clearly, the N/2-bit flash converters used in a half-flash converter have far fewer components than N-bit flash converters. However, the delay includes two flash converter delays and settling times for an N/2-bit D/A converter and an analog subtraction. Thus, a half-flash converter for a suitable N may have lower implementation cost than a corresponding flash converter, but also a slower speed. On the other hand, the N/2-bit flash converters and the N/2-bit D/A converter may have greater implementation cost than an N-bit D/A converter, while being used each once rather than N times. Thus, a half-flash converter may have higher overall implementation cost than that of a corresponding N-bit SA converter, but also a faster speed.
There are other prior art A/D conversion techniques. In techniques based on integration, the time required to charge or to charge and discharge capacitors with reference currents or unknown input-proportional currents is measured using digital counters. Counter outputs are the digital number outputs of the converters. Discrete charge-balancing techniques include delta-sigma A/D conversion and switched-capacitor A/D conversion. In each of these discrete techniques, small packets of charge are selectively applied so as to cancel out the effects of an analog input on an integrator circuit. A counter keeps track of the number of charge packets applied, which is the converter output at the end of the full conversion cycle.
In addition to the number of output bits provided by an A/D converter and the conversion speed, there are a variety of other design issues which are system-dependent. An A/D converter has an allowed range of analog input values. These should be well-matched to the transducers or sensors whose outputs are being converted. Also, it may be desired for the A/D converter to be incorporated on the same chip as other circuitry. A small number of A/D components may be desirable, but it may also be desired that these components be of similar construction to the components of the other circuitry. Also, it may be desired that the components consume a small amount of power.
As an example of a particular system, consider a digital image acquisition device such as a digital camera. The imaging sensors may form an array of 1200 elements by 1000 elements, for a total of 1.2 million sensors. To form a digital image, an output from each sensor must be converted to a corresponding digital number value. In order to allow timely re-use of the imaging array, all 1.2 million conversions should be carried out quickly, perhaps necessitating a single very fast A/D converter or a set of slower A/D converters operating in parallel. It may be desired that the imaging array and processing circuitry be on a single small chip so that the camera is physically very small and can be cheaply manufactured. However, the design may also require long operation time with a low-capacity battery as a power supply.
The principle disadvantages of prior art flash A/D converters are that while they are fast, they typically need a large number of components which use a great deal of chip space and which consume a large amount of power. The exponential increase in component counts and power consumption of flash converters limits the number of bits for which such converters are economically feasible to use. The principle disadvantages of SA A/D converters are that while they have low component cost and are economical for higher precision than are flash converters, they are quite slow and make inefficient use of the resources consumed. Half-flash converters combine the advantages and disadvantages of flash and SA converters. However, there is still plenty of room for alternative conversion techniques which are fast and which have low complexity.
The present invention is a type of analog-to-digital converter in which a series of flash converters are used to undertake a fast tree search over possible digital output numbers, with efficient generation of analog reference signals for each stage.
There are several objects and objectives of the present invention.
It is an object of the present invention to provide an A/D converter which has a much smaller component cost in terms of count and power consumption than comparable prior art flash or half-flash A/D converters.
It is an object of the present invention to provide an A/D converter which has a much faster conversion time than comparable prior art SA A/D converters.
It is an object of the present invention to provide for a class of A/D converters in which it is possible to selectively trade off overall component cost and speed, leading to a variety of designs of various precision, speeds, and costs.
It is an object of the present invention to provide low-cost, high-speed A/D converters for applications such as digital image acquisition or digital video acquisition in which it is necessary to carry out massive numbers of A/D conversions on a block-by-block or frame-by-frame basis.
It is an object of the present invention to provide a pipelined simultaneous A/D converter in which conversion of one analog input to the corresponding digital output may proceed relatively slowly, but in which the conversion rate approximates that of a flash A/D converter with an implementation cost less than that of an SA A/D converter.
Further objects and advantages of the invention will become apparent from a consideration of the ensuing description.